1. Field of the Invention
The present invention generally relates to a frequency synthesizer and a control method thereof having a function for calibrating an oscillation frequency, and more particularly, to an apparatus for frequency calibration in a frequency synthesizer and a control method thereof. The apparatus for frequency calibration in the frequency synthesizer and the control method thereof are utilized in a phase locked loop and remove a loop switch which is utilized for selecting a Vref voltage to be an input in an open loop status. In the apparatus and the method thereof, a charge pump directly outputs a GND voltage or a VDD voltage in the open loop status to decrease phase noise. When a memory bank which corresponds to a target frequency is selected, a memory bank offset compensation is performed according to a GND mode or a VDD mode.
2. Description of Prior Art
In a general situation, a phase locked loop (PLL) compares a phase of an input frequency with a phase of a feedback frequency, and then a locking frequency is controlled by a step-up/step-down charging method.
FIG. 1 shows a controlling circuit diagram of a conventional PLL. As shown in FIG. 1, the PLL comprises a reference frequency divider 1 for adjusting an input frequency, a phase detector 2 for comparing a phase of the input frequency with a phase of a feedback frequency, a charge pump 3 for generating a step-up/step-down voltage in accordance with the phase difference detected by the phase detector 2, a loop switch 4 for selecting either the step-up/step-down voltage in a close loop status or a Vref voltage in an open loop status, a loop filter 5 for removing noise resulting from the voltage which is selected by the loop switch 4, a voltage-controlled oscillator (VCO) 6 for controlling an oscillation frequency according to an output voltage of the loop filter 5, a VCO memory bank 7 for setting the oscillation frequency of the VCO 6, a pre-scaler 8 for dividing the oscillation frequency which is oscillated by an integer factor of the VCO 6, a programmable frequency divider 9 for dividing the frequency which is divided by the pre-scalar and oscillated to be the target frequency in the VCO 6 and a calculation value and feeding the calculation value back to the phase detector 2, a frequency comparator 10 for comparing the frequency outputting from the pre-scaler 8 with the target frequency, and a memory bank selector 11 for selecting the VCO memory bank 7.
When the conventional PLL (PLL circuits) as mentioned above is calibrated in the initial open loop status, the Vref voltage (for example, VDD/2) is inputted from the loop switch 4 to the VCO 6 via the loop filter 5, and the output frequency of the VCO 6 is proportionally oscillated by the Vref voltage. Then, after the frequency comparator 10 compares the output frequency with the target frequency, the memory bank selector 11 selects a memory bank that is closest to a compared result, whereby the programmable frequency divider 9 can divide the frequency as the calculation value which can be oscillated as the target frequency, and the calculation value is fed back to the phase detector 2.
The VCO memory bank 7 can be utilized and disposed in a capacitor array of the VCO 6 or in a PLL system without a structure of a memory bank. To have a broader band and a low phase noise, it's better for the VCO 6 of the PLL which is utilized in a wireless transceiver system or in a general situation to have a small gain value (Kvco). The VCO 6 comprises the capacitor array to form a structure of a memory bank so as to decrease the gain value (Kvco).
The phase detector 2 detects the phase difference between the output frequency of the reference frequency divider 1 and the output frequency of the programmable divider 9, and then the phase detector 2 generates the step-up/step-down voltage (Vc) to the charge pump 3 according to the phase difference. The output of the charge pump 3 is selected by the charge pump 3 and inputted to the VCO 6 via the loop filter 5 to be a control voltage. The VCO 6 controls the oscillation frequency proportional to the control voltage (Vc) which is corresponding to the phase difference. By doing so, the oscillation frequency is controlled according to the phase difference to select the final memory bank for implementing a frequency locked function.
When a new frequency is locked in the conventional PLL, the VCO 6 performs the oscillation operation after the loop switch 4 selects the Vref voltage to fix the control voltage. The memory bank selector selects the required memory bank to implement PLL lock in the close loop status. However, the conventional PLL comprises the loop switch 4, and the control voltage is inputted to the VCO 6 by the loop switch 4. Accordingly, a problem of phase noise occurs because the loop switch 4 utilizes COMS switches. Furthermore, there also exists a disadvantage of requiring a circuit for generating the Verf voltage.